What is a Register-Register (RISC) architecture?
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An architecture that can access memory only via load and store instructions.
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What is a Register-Register (RISC) architecture?
An architecture that can access memory only via load and store instructions.
What is the maximum memory capacity of the MIPS 32 processor?
Up to 2^32 bytes, which equals 2^30 words.
What does Instruction Set Architecture (ISA) represent?
WHAT the computer does (logical view).
What are the two early types of instruction set architectures?
Accumulator-based and Stack-based.
What is Register Addressing in MIPS?
Where the operand is a register (R - Type).
How many addressing modes does the Intel 80386 support?
12 addressing modes.
What defines Immediate Addressing in MIPS?
Where the operand is a constant in the instruction (I - Type, ALU).
What is the primary feature of MIPS 32 Architecture?
It utilizes a RISC (Reduced Instruction Set Computer) design.
What is a Register-Memory (CISC) architecture?
An architecture that can access a memory location as part of any instruction.
Why do general purpose registers dominate in computer architecture?
They provide flexibility and efficiency in data processing and instruction execution.
What does Computer Organization represent?
HOW the ISA is implemented (physical view).
What are the components included in an ISA?
Instructions and Instruction Formats, Data Types, Encodings, and Representations, Programmable Storage, Addressing Modes, and Handling Exceptional Conditions.
What replaced accumulator and stack-based architectures?
General-Purpose Register (GPR) architectures.
What are the possible operand sizes in the Intel 80386?
8, 16, 32, 48, 64, or 80 bits long.
What is a Memory-Memory architecture?
An architecture that can access two or three memory locations per instruction, not used today.
What is included in the I-Type instruction format?
A 16-bit immediate constant.
How do you convert the jump target in words to bytes?
Multiply the jump target by 4.
What is the maximum size of an instruction in the Intel 80386?
12 bytes long.
What does 'sw 2)' accomplish?
Stores the word in register 2 plus an offset of 0.
What do improved technologies enable?
They make new applications possible.
What is one advantage of having an ISA?
Different implementations of the same architecture.
What is the width of all instructions in MIPS 32 Architecture?
32 bits.
What is Computer Architecture?
Computer Architecture = Instruction Set Architecture + Computer Organization.
What is the opcode for the Jump (j) instruction in MIPS J-Type?
2
What does MIPS stand for in MIPS 32 Architecture?
Microprocessor without Interlocked Pipelined Stages.
Why is an ISA easier to change than hardware?
Because it standardizes instructions and machine language bit patterns.
What is a disadvantage of an ISA?
It sometimes prevents using new innovations.
What is the common definition of memory in most architectures?
Memory is defined as byte addressable.
What is the role of the Instruction Set Architecture (ISA)?
The ISA forms an abstraction layer that sets the requirements for both compiler and CPU designers.
How does architecture influence software development?
It is continually changing.
What is an example of a CISC ISA?
Intel 80386.
What is the opcode for the Jump and Link (jal) instruction in MIPS J-Type?
3
What is the purpose of the MIPS register file?
To store and manage the general-purpose registers used in MIPS architecture.
What does the R-Type instruction format primarily involve?
Register-to-register instructions.
What is the size of the smallest instruction in the Intel 80386?
One byte.
How many general-purpose registers does the MIPS architecture have?
32 general-purpose registers.
What is a characteristic of Memory-Memory architecture?
It has a large variation in instruction size and work per instruction (CPI).
What is the purpose of the 'rt' field in MIPS R-Type instructions?
It represents the second register source operand.
What is the typical use of general purpose registers in a CPU?
To store temporary data and intermediate results during computations.
What are typical operations in computer architecture?
Basic actions performed by a computer, such as arithmetic, logic, control, and data transfer.
What is the purpose of the jump target in MIPS J-Type instructions?
It specifies the jump memory address in words.
What does the instruction 'lw 2)' do?
Loads a word from memory into register 2 plus an offset of 0.
What does a logic operation entail?
Operations that involve Boolean logic, such as AND, OR, NOT.
How many addressing modes are available in MIPS 32 Architecture?
Five addressing modes.
What do the first bytes of an instruction generally contain?
Opcode, mode specifiers, and register fields.
What is the function of the ALUOP control signal?
It determines the operation performed by the ALU based on the instruction.
How is word size defined differently by architectures?
Word size can be 2 bytes (Intel x86), 4 bytes (MIPS), or larger.
What is the role of an assembler?
To convert assembly language programs into machine language.
What is the opcode for load operations in MIPS?
Which architectures use hybrid encoding?
Micro MIPS and ARM Thumb.
What is the function of the $gp register?
It is the global pointer that points to global data.
How does instruction encoding impact computer architecture?
It impacts size and ease of decoding.
What does R-type instruction format represent?
It is used for register-based operations.
What are general purpose registers?
Registers that can hold data, addresses, or instructions and are used for various operations in a CPU.
What does ISA stand for?
Instruction Set Architecture.
What is the purpose of an Instruction Set Architecture?
It serves as an abstract interface between hardware and the lowest-level software.
What is Base or Displacement Addressing?
Where the operand is at the memory location whose address is the sum of a register and a constant in the instruction (I - Type, load/store).
What is Pseudodirect Addressing in MIPS?
Where the jump address is the 26-bit jump target from the instruction shifted left 2 bits concatenated with the 4 upper bits of the PC (J - Type).
What are the names of the special registers in the MIPS 32 architecture?
1, 31, Hi, Lo.
What is the purpose of the J-Type instruction format?
Used by jump instructions.
What is the size of the jump target field in MIPS J-Type instructions?
26 bits
Name three addressing modes supported by the Intel 80386.
Register, Immediate, Direct.
How is the effective 32-bit jump address calculated in MIPS?
PC(31-28), jump_target, 00
What is the significance of pipelining in MIPS 32 Architecture?
Pipelining allows multiple instruction phases to be processed simultaneously, improving performance.
What is the purpose of a compiler in programming?
To translate high-level language programs into machine language.
How do Register-Register architectures compare to Register-Memory architectures?
Register-Register architectures are simpler.
What is the size of the data bus in MIPS 32 Architecture?
32 bits.
What can a memory address provide access to?
A byte, 2 bytes, 4 bytes, 8 bytes, or more bytes.
What is the role of the $zero register in MIPS?
It always holds the value 0 and cannot be modified.
What does the 'rt' field indicate in MIPS Branch I-Type instructions?
It indicates the second register being compared.
What role do applications play in technology development?
They suggest improvements and provide revenue to fund development.
How do general purpose registers improve performance?
By reducing the need to access slower memory, allowing faster data retrieval and manipulation.
What will be studied in this course?
Both Instruction Set Architecture and Computer Organization.
What is a major reason for using General-Purpose Registers (GPR) architectures?
Registers are faster than memory and reduce memory traffic.
Why are General-Purpose Registers easier for compilers to use?
Because they provide a simpler interface for instruction generation.
What does the 'op' field represent in MIPS R-Type instructions?
Opcode, which indicates the basic operation of the instruction.
What is the purpose of the $zero register in MIPS?
It always holds the value 0, forced by hardware.
What effect do aligned memory references have on program performance?
Programs with aligned memory references run faster.
What is the size of each register in the MIPS architecture?
Each register is 32 bits in size.
What is the function of the Floating Point Unit (FPU) in MIPS 32?
It handles floating-point arithmetic operations.
What are the fields in the R-Type instruction format?
Op, Rs, Rt, Rd, funct, and sa.
What are the three instruction formats in a 32-bit instruction set?
Register (R-Type), Immediate (I-Type), and Jump (J-Type).
What does I/O system refer to in computer architecture?
It refers to the input/output system that manages data exchange between the computer and external devices.
What is variable encoding in instruction sets?
Instruction length is a variable number of bytes, allowing all addressing modes to be used with all operations.
What is the value of 'op' for R-Type instructions in MIPS?
What does CISC stand for?
Complex Instruction Set Computer.
What registers are used for function result values in MIPS?
v1.
What is a data transfer operation?
Operations that move data between registers, memory, and I/O devices.
What do addressing modes specify?
Registers, constants, and memory locations.
What are the two types of registers in the MIPS register file?
General-purpose registers and special-purpose registers.
What are General Purpose Registers (GPRs) used in MIPS?
32-bit registers.
What is the purpose of the 'rs' field in an I-Type ALU instruction?
It is the register source operand.
What do addressing modes specify in instructions?
The addresses of their operands.
What is the purpose of the Integer Multiplier/Divider in MIPS 32?
To perform multiplication and division operations on integers.
How does RISC handle memory operations?
'LOAD' and 'STORE' are independent instructions (register to register).
What does the $ra register store?
The return address used by the jal instruction for function calls.
What is the function of register $sp in MIPS?
It is the stack pointer.
How can an assembler refer to registers in MIPS?
By name or by number; using names is easier to remember.
What does Absolute addressing mode specify?
Accessing a fixed memory address, e.g., LD R1, [1000] means R1 = Mem[1000].
How many bytes are there per word in the MIPS 32 architecture?
4 bytes per word.
How does PC-Relative Addressing work in MIPS?
Where the address is the sum of the PC and the 16-address field in the instruction shifted left 2 bits (I - Type, branches).
What are the categories of instructions in MIPS 32 Architecture?
Load/Store, Integer Arithmetic, Jump and Branch, Floating Point, Memory Management.
How many general-purpose registers does the MIPS 32 processor have?
32 general-purpose registers.
What is the role of the instruction set in MIPS 32 Architecture?
It defines the operations that the processor can perform.
What is Little Endian byte ordering?
Memory address X is the address of the least-significant byte (Intel x86).
Which registers are used for function arguments in MIPS?
a3.
What does 'rd' signify in MIPS R-Type instructions?
The register destination operand.
What is the width of all registers in MIPS?
32 bits.
What fields are included in the J-Type instruction format?
Op and immediate.
What do the special-purpose registers LO and HI hold?
Results of integer multiply and divide.
What is the purpose of the instruction 'sw 2)'?
It stores the value in register 2 plus an offset of 4.
What are registers 23 called in MIPS?
s7, used for saved values.
What is the purpose of the Immediate addressing mode?
To use constants directly in operations, e.g., ADD R1, R2, 100 means R1 = R2 + 100.
How many Floating Point Registers (FPRs) are there in MIPS?
32 Floating Point Registers.
What is the cycle speed and code size characteristic of RISC?
Low cycles per second with large code sizes.
What is the bit size of Floating Point Registers in MIPS?
They can be either 32-bit or 64-bit.
What is the size of a single-precision float?
4 bytes (32 bits).
What is the size of a double-precision float?
8 bytes (64 bits).
What is an arithmetic operation?
Operations that involve mathematical calculations like addition, subtraction, multiplication, and division.
How many general-purpose registers does MIPS 32 Architecture have?
32 general-purpose registers.
How many instruction formats are there in MIPS 32 Architecture?
Three instruction formats.
What does the 'op' field represent in MIPS Branch I-Type instructions?
Opcode, operation of the instruction.
What are the two types of J-Type instructions in MIPS?
Jump (j) and Jump and Link (jal).
Which architectures use variable encoding?
Intel x86 and VAX.
What is the significance of firmware in computer architecture?
Firmware provides low-level control for a device's specific hardware.
What does the assembly instruction 'temp = v[k];' represent in machine language?
It corresponds to loading a value from an array into a temporary variable.
What is included in the remainder bytes of an instruction?
Address displacement and immediate data.
What does the 'op' field represent in an I-Type instruction?
Opcode, operation of the instruction.
Name a common addressing mode used in MIPS.
Immediate addressing mode.
In a 32-bit register using Little Endian, how are the bytes ordered?
Byte 0 is at address x, Byte 1 at x+1, Byte 2 at x+2, and Byte 3 at x+3.
What is the value of Register 0 in MIPS?
Always zero; any value written to R0 is discarded.
How does CISC handle memory operations?
It incorporates 'LOAD' and 'STORE' in instructions (memory-to-memory).
What is the purpose of digital design in computer architecture?
Digital design focuses on the design of circuits and systems that process digital signals.
What are registers 15 used for in MIPS?
They are called t7 and are used for temporary values.
What is the opcode for store operations in MIPS?
What is the function of a BIOS?
BIOS (Basic Input/Output System) initializes and tests hardware components during the booting process.
How is the offset in MIPS Branch I-Type instructions calculated?
It is equal to the instruction address field multiplied by 4.
What is the format of the R-Type instruction fields?
op (6 bits), rs (5 bits), rt (5 bits), rd (5 bits), shamt (5 bits), funct (6 bits).
What does the 'address' field represent in MIPS Load/Store I-Type instructions?
A 16-bit memory address offset in bytes added to the base register.
What is an example of an I-Type ALU instruction for bitwise AND?
andi 2, 10.
What is the size of an extended-precision float?
10 bytes (80 bits).
What does 'rs' represent in MIPS R-Type instructions?
The first register source operand.
What are the types of instruction formats in MIPS 32?
R-type, I-type, J-type.
What is the purpose of the PC register in MIPS 32 Architecture?
It holds the address of the next instruction to be executed.
What is the maximum addressable memory with 32 bits?
4 GB.
What is Register Transfer Notation (RTN)?
RTN is a method for describing the operations of a computer's registers and data transfer.
What does the 'op' field represent in MIPS Load/Store I-Type instructions?
Opcode, which indicates the operation of the instruction.
What are the components of the MIPS 32 processor's memory unit?
Trap & Memory Unit (Coproc 0) and Floating Point Unit (Coproc 1).
What is the purpose of instruction formats in MIPS?
Instruction formats define the layout of bits in an instruction.
What does the 'rt' field indicate in an I-Type instruction?
The result destination register.
What does the Register addressing mode do?
Adds values in registers, e.g., ADD R1, R2, R3 means R1 = R2 + R3.
What is the bit size of the 'rs' and 'rt' fields in an I-Type instruction?
5 bits each.
How are double-precision floating-point values stored in MIPS?
Using a pair of registers.
What is the $at register reserved for?
Assembler use.
What is the role of the ALU in the MIPS 32 processor?
It performs arithmetic and logic operations.
What is the purpose of the 'rs' field in MIPS Branch I-Type instructions?
It represents the first register being compared.
What are the fields in an I-Type ALU instruction?
op, rs, rt, immediate.
How many General Purpose Registers (GPRs) are there in MIPS?
32 General Purpose Registers.
What notation does the assembler use to name registers in MIPS?
Dollar notation (e.g., 1, ..., $31).
What is Big Endian byte ordering?
Memory address X is the address of the most-significant byte (SPARC).
What are the register names in MIPS 32 Architecture?
R0 to R31, PC, HI, LO.
What are high-level language programs?
Programs written in a programming language that is more abstract and easier for humans to understand.
What type of instructions are most frequently used?
The simplest ones.
In a 32-bit register using Big Endian, how are the bytes ordered?
Byte 0 is at address x+3, Byte 1 at x+2, Byte 2 at x+1, and Byte 3 at x.
How many main instruction formats are there in MIPS?
Three main formats: R-type, I-type, and J-type.
What is the function of the special-purpose program counter (PC)?
It keeps track of the address of the next instruction to be executed.
What does the 'rs' field represent in MIPS Load/Store I-Type instructions?
The register containing the memory base address.
What addressing mode is used in MIPS Branch I-Type instructions?
PC-Relative Addressing.
What is the size of a Unicode character or short integer?
2 bytes (16 bits).
How does Indexed addressing mode work?
Combines a base address and an index, e.g., LD R1, [R2, R3] means R1 = Mem[R2 + R3].
What is the purpose of Scaled Index addressing mode?
To use a scale factor with an index, e.g., LD R1, [R2, R3, s] means R1 = Mem[R2 + R3 << s].
What is the function of Post-update addressing mode?
Updates the address after accessing memory, e.g., LD R1, [R2], 8 means R1 = Mem[R2] and R2 = R2 + 8.
What is the relationship between compilers and the ISA?
The ISA defines the requirements that compilers must adhere to for effective communication with the CPU.
What is the consequence of misalignment in memory references?
It requires multiple aligned memory references.
What is a key characteristic of CISC architecture?
It includes multi-clock complex instructions.
What are addressing modes in MIPS?
Addressing modes determine how the operand of an instruction is accessed.
What is the size of the 'address' field in MIPS Branch I-Type instructions?
16 bits.
What is the function of the 'shamt' field in MIPS R-Type instructions?
It indicates the shift amount used in constant shift operations.
What does the 'funct' field do in MIPS R-Type instructions?
It selects the specific variant of operation in the op field.
What is the instruction format for 'Branch on Not Equal' in MIPS?
bne 2, 100.
How does instruction encoding impact processor performance?
It affects code size and ease of decoding inside the processor.
What does the $sp register indicate?
The stack pointer, which points to the top of the stack.
What is the role of the $fp register?
It is the frame pointer, which points to the current stack frame.
How many ASCII characters can a 64-bit register store?
8 characters.
How do CISC and RISC differ in transistor usage?
CISC uses transistors for storing complex instructions, while RISC spends more transistors on memory registers.
What is the format for a load word instruction in MIPS?
lw 2).
What is the maximum memory addressable by 32-bit architectures?
4 GB.
What is a control operation?
Operations that manage the flow of execution in a program, such as branching and looping.
What type of instructions does MIPS 32 Architecture primarily use?
Load/store instructions for data manipulation.
What is MIPS?
MIPS stands for Microprocessor without Interlocked Pipeline Stages, a type of computer architecture.
What is fixed encoding in instruction sets?
All instructions have a single fixed size, typically 32 bits, combining the addressing mode with the opcode.
What does the term 'Software/Hardware Boundary' refer to?
It refers to the interface between software and hardware components in a computer system.
What is the purpose of the control unit in MIPS 32 Architecture?
To direct the operation of the processor and coordinate the execution of instructions.
What fields are present in the I-Type instruction format?
Op, Rs, Rt, and immediate.
What is the range of temporary registers in MIPS?
t7.
What is the function of the address field in MIPS Branch I-Type instructions?
It is a branch target offset added to the PC to form the branch address.
What do the $s registers represent in MIPS?
Saved registers that are preserved across function calls.
What is the instruction format for 'Branch on Equal' in MIPS?
beq 2, 100.
What is the bit size of the 'op' field in an I-Type instruction?
6 bits.
What is the purpose of the 'rt' field in MIPS Load/Store I-Type instructions?
For loads, it is the destination register; for stores, it is the source register of the value to be stored.
What does J-type instruction format represent?
It is used for jump instructions.
What does register $ra represent in MIPS?
It is the return address register.
What type of addressing mode is used in I-Type instructions?
Immediate Addressing (Mode 2).
What is the size of a quad-precision float?
16 bytes (128 bits).
What does RISC stand for?
Reduced Instruction Set Computer.
What does the Execution & Integer Unit in MIPS 32 do?
It executes integer operations and manages the main processing.
What is the significance of the binary instruction '1000110001100010000000000000000'?
It represents a specific machine language instruction in binary format.
What is hybrid encoding in instruction sets?
It features few instruction lengths to reduce variability and includes compressed encoding of frequently used instructions.
What is special about register $0 in MIPS?
Register $0 is always zero; any value written to it is discarded.
What does the instruction 'v[k] = v[k + 1];' do in assembly language?
It assigns the value of the next element in the array to the current element.
What does the 'immediate' field represent in an I-Type ALU instruction?
Constant second operand for ALU instruction.
What is the I-type instruction format used for?
It is used for immediate values and memory access.
What is the function of Displacement addressing mode?
Accessing memory with an offset, e.g., LD R1, [R2, 8] means R1 = Mem[R2 + 8].
What is the size of an integer in bytes?
4 bytes (32 bits).
What does Pre-update addressing mode do?
Updates the address before accessing memory, e.g., LD R1, [R2, 8]! means R2 = R2 + 8 and R1 = Mem[R2].
Which architectures use fixed encoding?
MIPS, ARM, Power, SPARC, etc.
Which registers are used for function return values in MIPS?
The v1 registers.
What is a defining feature of RISC architecture?
It utilizes a small, highly-optimized set of instructions.
What is the maximum addressable memory with 64 bits?
16 Exabytes.
What is the function of the $sp register in MIPS?
It serves as the stack pointer.
What are the possible locations for operands?
Registers, constants, or in memory.
What type of instructions does R-Type encompass in MIPS?
All ALU instructions that use three registers.
What is the cycle speed and code size characteristic of CISC?
Small code sizes with high cycles per second.
What is the purpose of defining names for all registers in MIPS?
To standardize their use in programs.
What is the size of an ASCII character in bytes?
1 byte.
What does Register Indirect addressing mode involve?
Using the address contained in a register, e.g., LD R1, [R2] means R1 = Mem[R2].
What does R-Type stand for?
Register Type.
What is the bit size of the 'immediate' field in an I-Type instruction?
16 bits.
What is the format for a store word instruction in MIPS?
sw 4).
What addressing mode is used in MIPS Load/Store I-Type instructions?
Base or Displacement Addressing (Mode 3).
What is VLSI placement and routing?
VLSI placement and routing involve arranging and connecting components on a chip to optimize performance.
What is an example of an I-Type ALU instruction for addition?
addi 2, 100.
What is the size of a long integer?
8 bytes (64 bits).
What do 64-bit architectures support?
64-bit operands and memory addresses.
What is a major force in the market for software development?
Compatibility.