x86-64 Assembly Language Programming with Ubuntu – chapter 7

The jne <label> instruction causes a jump to <label> if the preceding comparison indicates that <op1> != <op2>. The label must be defined exactly once in the code.

The j1 <label> instruction checks if <op1> < <op2> for signed data, and if true, it jumps to <label>. The label must be defined exactly once.

The operands in an instruction refer to where the data (to be operated on) is coming from and/or where the result is to be placed.

signifies a memory location, which may be a variable name or an indirect reference (i.e., a memory address).

Omitting the brackets will not access the memory; instead, it will obtain the address of the item. For example, 'mov rax, wNum' retrieves the address of 'wNum', while 'mov rax, word [wNum]' retrieves the value stored at that address.

The address of a variable can be obtained using the load effective address (lea) instruction, which allows the programmer to load the address of a variable into a register without accessing its value.

Narrowing conversions refer to converting from a larger type to a smaller type, such as from a word to a byte or from a double-word to a word. No special instructions are needed for these conversions, and the lower portion of the memory location or register can be accessed directly.

If a value that exceeds the target type's capacity is used in a narrowing conversion, it may lead to incorrect results. For example, storing the value 500 (0x1f4) in a byte will result in only the lower byte being stored, which can cause data loss or incorrect values.

Widening conversions refer to the process of converting a smaller data type to a larger data type (e.g., byte to word or word to double-word). During this conversion, the upper-order bits must be set based on the sign of the original value, requiring knowledge of whether the data type is signed or unsigned.

For unsigned widening conversions, the upper part of the memory location or register is set to zero, as unsigned values can only be positive. For example, to convert a byte value of 50 in the al register to a quadword value in rbx, the following operations can be performed:

1. mov al, 50
2. mov rbx, 0
3. mov bl, al

This sets the entire 64-bit rbx register to 50.

The movzx <dest>, <src> instruction is used for unsigned widening conversions (smaller → larger), filling the upper-order bits of the destination with zero. It is important to note that both operands cannot be memory, and it does not allow a quadword destination operand with a double-word source operand.

The destination operands for the movzx instruction cannot be an immediate value; they must be registers or memory locations.

Signed widening conversion involves a sign-extend operation where the upper-order bits of the new, widened value are set based on the upper-order bit of the original value. If the original value is positive, the upper bits are set to 0; if negative, they are set to 1.

The cwd instruction converts a signed value in the ax register into a double-word value in the dx (upper-order portion) and ax (lower-order portion) registers, typically represented as dx:ax.

The cwde instruction converts a signed value in the ax register into a double-word value in the eax register, allowing for a larger representation of the signed value.

The general forms of signed conversion instructions are

• movsx <destination>, <source>, for sign extension and

• movsxd <destination64>, <source32> , for sign extension with a quadword destination operand and a double-word source operand.

The cbw instruction converts a byte in the al register into a word in the ax register, and it only works for the al to ax conversion.

The cdq instruction converts a double-word in the eax register into a quadword in the edx:eax registers, specifically for the eax to edx:eax conversion.

The 'cdqe' instruction converts a double-word in the 'eax' register into a quadword in the 'rax' register. It only works for the 'rax' register.

The 'cqo' instruction converts a quadword in the 'rax' register into a double-quadword in the 'rdx:rax' registers. It only works for the 'rax' to 'rdx:rax' registers.

The 'movsx' instruction performs signed widening conversion via sign extension. It can convert smaller integer types to larger ones while preserving the sign.

1. Both operands cannot be memory.
2. Destination operands cannot be an immediate.
3. Immediate values are not allowed for certain conversions.
4. A special instruction 'movsxd' is required for 32-bit to 64-bit signed extension.

Explicit type specification is included for consistency and good programming practice. It can be omitted when the size of the other operand clearly defines the size of the operation.

The 'add' instruction adds two operands and places the result in the destination operand, overwriting its previous value.

The 'inc' instruction increments the specified operand by 1. The operand cannot be an immediate value.

When using the 'add' instruction, both operands cannot be memory, and the destination operand cannot be an immediate value. Additionally, 64-bit immediate values are not allowed.

The addition instruction operates the same on both signed and unsigned data types; it is the programmer's responsibility to ensure that the data types and sizes are appropriate for the operations being performed.

The add with carry instruction is used to include a carry from a previous addition operation, which is essential when adding very large numbers that exceed the register size of the machine.

The general form is: adc , , where is the destination operand and is the source operand, and the operation adds , , and the carry bit.

The destination and source operands must be of the same size, the destination operand cannot be an immediate value, and both operands cannot be memory; if memory to memory addition is needed, two instructions must be used.

128-bit values are split into two 64-bit parts. Each part is moved into separate 64-bit registers using two move instructions. For example:

1. mov rax, qword [dquad1] (loads the first 64-bits into rax)
2. mov rdx, qword [dquad1+8] (loads the next 64-bits into rdx)

The instruction 'adc , ' adds two operands, ( + ) and any previous carry (stored in the carry bit in the rFlag register), placing the result in (over-writing the previous value).

adc operand1, operand2 → operand1 = operand1 + operand2 + carry

The destination and source operands must be of the same size (both bytes, both words, etc.), the destination operand cannot be an immediate, and both operands cannot be memory. If a memory to memory subtraction operation is required, two instructions must be used.

The 'dec' instruction decreases the value of the specified operand by 1, effectively performing the operation: = - 1.

When using a memory operand with the 'dec' instruction, an explicit type specification (e.g., byte, word, dword, qword) is required to clearly define the size of the operand.

The 'sub' instruction is used to subtract one operand from another.

sub <dst>, <src> → dest = dest - src

The destination operand cannot be an immediate value, and it can involve memory or register operands.

The 'mul' instruction is used for unsigned multiplication, while the 'imul' instruction is used for signed multiplication. Both instructions multiply two integer operands, but they handle signed values differently.

Multiplying two n-bit values produces a 2*n-bit result. For example, multiplying two 8-bit numbers results in a 16-bit value, two 16-bit numbers yield a 32-bit result, and so on up to 128 bits for two 64-bit numbers.

In signed multiplication, some forms of the 'imul' instruction (2 and 3 operands form) may truncate the result to the size of the destination operands. It is the programmer's responsibility to ensure that the values used are appropriate for the specific instructions selected.

The 'mul' instruction multiplies the A register (al, ax, eax, or rax) by the operand, with the result stored in the appropriate registers based on the operand size.

The general form is mul <src>, where <src> must be a register or memory location, and an immediate operand is not allowed.

mul <src> → D:A = A reg * <src>

The A register (al/ax/eax/rax) must be used as one of the operands, depending on the size: al for 8-bits, ax for 16-bits, eax for 32-bits, and rax for 64-bits.

The result is stored in the A and possibly D registers, depending on the sizes being multiplied.

This practice is due to legacy support for earlier versions of the architecture, ensuring backwards compatibility, although it can be confusing.

The format for the 'imul' instruction with two operands is:

imul <dst>, <src/imm>

<dest> = <dest> * <src/imm>

Here, the destination operand is multiplied by the source operand or immediate value, and the result is stored in the destination operand, overwriting its previous value.

For the 'imul' instruction, the size of the <src/imm> value is limited to the size of the source operand, up to a double-word size (32-bit), even for quadword (64-bit) multiplications.

The final result is truncated to the size of the destination operand. A byte sized destination operand is not supported.

The operand must be a register or memory location (not an immediate), while the operand must be an immediate value.

The size of the immediate value is limited to the size of the source operand, up to a double-word size (32-bit), even for quadword multiplications.

The least significant double-word of the quadword will contain the answer if the values multiplied fit into the smaller size.

You would multiply the value of wNumA (1200) by -13 and store the result in wAns1.

The example data declarations illustrate how to perform basic multiplication operations using different data sizes in x86-64 assembly language.

1. Load wNumA into ax using mov ax, word [wNumA].
2. Multiply ax by -13 using imul ax, -13.
3. Store the result in wAns1 using mov word [wAns1], ax.

1. Load dNumA into eax using mov eax, dword [dNumA].
2. Multiply eax by 113 using imul eax, 113.
3. Store the result in dAns1 using mov dword [dAns1], eax.

1. Load qNumA into rax using mov rax, qword [qNumA].
2. Multiply rax by 7096 using imul rax, 7096.
3. Store the result in qAns1 using mov qword [qAns1], rax.

1. Load wNumA into ax using mov ax, word [wNumA].
2. Multiply ax by wNumB using imul ax, word [wNumB].
3. Store the result in wAns2 using mov word [wAns2], ax.

1. Load dNumA into eax using mov eax, dword [dNumA].
2. Multiply eax by dNumB using imul eax, dword [dNumB].
3. Store the result in dAns2 using mov dword [dAns2], eax.

The imul instruction is used to perform signed multiplication of integers, allowing for multiplication of different data sizes (word, double, quad) as demonstrated in the code snippets.

The 'imul' instruction is used for signed multiplication in assembly language, allowing for various operand configurations such as single, two, or three operands.

The multiplication result is truncated to the size of the destination operand. For a full-sized result, a single operand instruction should be used instead.

The 'imul' instruction can be used in several configurations:

1. Single Operand: imul <src>
2. Two Operands: imul <dest>, <src/imm32> or imul <reg>, <op>
3. Three Operands: imul <reg>, <op>, <imm>

Each configuration allows for different sizes of operands, such as byte, word, dword, and qword.

The explicit type specification (e.g., byte, word, dword, qword) may not be required for some instructions, but it helps to clearly define the size of the operands being used in the multiplication operation.

Using a 64-bit immediate value with the 'imul' instruction is not allowed; the instruction does not support immediate values of that size.

• Unsigned Division: div
• Signed Division: idiv

The dividend must be a larger size than the divisor:

• An 8-bit divisor requires a 16-bit dividend.
• A 16-bit divisor requires a 32-bit dividend.
• A 32-bit divisor requires a 64-bit dividend.

• Byte Divide: ax for 16-bits
• Word Divide: dx:ax for 32-bits
• Double-word Divide: edx:eax for 64-bits
• Quadword Divide: rdx:rax for 128-bits

A key source of problems is setting the dividend (top operand) correctly, especially for word, double-word, and quadword division operations, which require both the D register (for the upper-order portion) and A register (for the lower-order portion).

The upper portion of the D register will always be zero when unsigned data is placed in it.

The result of a division operation is stored in the A register (al/ax/eax/rax).

Dividing by zero will crash the program and damage the space-time continuum.

The existing data must be sign extended for signed data before division.

The remainder can be placed in either the ah, dx, edx, or rdx register.

An appropriate conversion may be required to ensure the dividend is set correctly for simple divisions.

The general forms are:

• div <src> for unsigned division
• idiv <src> for signed division

The programmer is responsible for ensuring that the values being divided are appropriate for the operand sizes being used.

The data declarations include:

• Byte (db): bNumA, bNumB, bNumC, bAns1, bAns2, bRem2, bAns3
• Word (dw): wNumA, wNumB, wNumC, wAns1, wAns2, wRem2, wAns3
• Double Word (dd): dNumA, dNumB, dNumC, dAns1, dAns2, dRem2, dAns3
• Quad Word (dq): qNumA, qNumB, qNumC, qAns1, qAns2, qRem2, qAns3

The result is stored in bAns1 after dividing the value of bNumA by 3 using unsigned division.

The modulus operation is represented by the '%' symbol, and the remainder is stored in the ah register after a division operation.

The instruction used is 'div byte [bNumB]', which divides the value in ax by the value in bNumB.

The 'mul' instruction is used to multiply bNumA by bNumC, with the result stored in the ax register before performing the division by bNumB.

The 'mov' instructions are used to load values into registers before performing arithmetic operations, ensuring the correct values are used in calculations.

The 'div' instruction performs unsigned division, dividing the value in the accumulator (AX or EAX) by the specified operand, and stores the quotient in the accumulator and the remainder in DX or EDX.

The remainder is obtained from the DX register after executing the 'div' instruction for unsigned division or from the EDX register for signed division.

The 'div' instruction is used for unsigned division, while the 'idiv' instruction is used for signed division, affecting how the dividend is interpreted and how the quotient and remainder are calculated.

The 'cdq' instruction extends the sign of EAX into EDX, preparing the registers for signed division by ensuring that the dividend is correctly represented in the combined EDX:EAX register pair.

This operation first multiplies 'wNumA' by 'wNumC' to get a double-word result in DX:AX, and then divides that result by 'wNumB', storing the quotient in 'wAns3'.

The 'imul' instruction is used to perform signed multiplication. In the provided example, it multiplies the value in 'dNumA' by 'dNumC', with the result stored in the registers 'edx' and 'eax'.

The 'idiv' instruction is used for signed division. It divides the value in 'edx:eax' by the specified operand (e.g., 'dNumB' or 'rbx') and stores the quotient in 'eax' and the remainder in 'edx'.

The 'cqo' instruction is used to sign-extend the value in 'rax' to 'rdx:rax' before division. This is important for ensuring that the division operation correctly handles signed values.

The operation 'qAns1 = qNumA / 9' performs signed division of 'qNumA' by 9, storing the quotient in 'qAns1'. The 'cqo' instruction is used to prepare for the division by extending 'rax' to 'rdx:rax'.

The operation 'qAns3 = (qNumA * qNumC) / qNumB' first multiplies 'qNumA' by 'qNumC' using 'imul', then divides the result by 'qNumB' using 'idiv', storing the quotient in 'qAns3'.

The 'div' instruction performs an unsigned division of the A/D register (ax, dx:ax, edx:eax, or rdx:rax) by the operand. The result is stored in the A/D register, and the remainder is stored in a specific register depending on the size of the operation:

• Byte: al = ax / , remainder in ah
• Word: ax = dx:ax / , remainder in dx
• Double: eax = edx:eax / , remainder in edx
• Quad: rax = rdx:rax / , remainder in rdx

Note: The operand cannot be an immediate value.

The 'div' instruction is used for unsigned division, while the 'idiv' instruction is used for signed division. Both instructions divide the A/D register by the operand, but 'idiv' takes into account the sign of the numbers involved, affecting the result and remainder accordingly.

The basic logical operations are AND, OR, and XOR. Their truth tables are as follows:

AND:

OR:

XOR:

Shift operations are used to isolate a subset of bits within an operand or to perform multiplication or division by powers of two. All bits are shifted one position, with the bit that is shifted out being lost and a 0-bit added at the other side.

A logical shift operation shifts all bits of its source register by a specified number of bits, placing the result into the destination register. The bits can be shifted left or right, and the newly vacant positions are filled with zeros.

In a right logical shift, bits are shifted to the right, dropping the rightmost bit and inserting a 0 at the leftmost position. In a left logical shift, bits are shifted to the left, dropping the leftmost bit and inserting a 0 at the rightmost position.

Logical shift operations can be used to perform unsigned integer multiplication and division by powers of 2, such as dividing by 2 or multiplying by 4, by shifting bits accordingly.

The shl instruction performs a logical shift left operation on the destination operand, filling the vacated bit locations on the right with zeros. The immediate value or the value in the cl register must be between 1 and 64, and the destination operand cannot be an immediate value.

The shr instruction performs a logical shift right operation on the destination operand, filling the vacated bit locations on the left with zeros. The immediate value or the value in the cl register must be between 1 and 64, and the destination operand cannot be an immediate value.

The immediate value used in both shl and shr instructions must be between 1 and 64, and only 8-bit immediate values are allowed. Additionally, the destination operand cannot be an immediate value.

In logical shift operations, a 0 is entered in the newly vacated bit locations, either on the right for shl (shift left) or on the left for shr (shift right).

The arithmetic shift right operation shifts all bits of its source register by a specified number of bits, placing the result into the destination register. It replicates the original leftmost bit (the sign bit) to fill in the newly vacant positions, a process known as sign extension.

The arithmetic left shift operation moves bits to the left by a specified number of positions and zero fills from the least significant bit position. Unlike the right shift, the leading sign bit is not preserved, and it can be used for efficient multiplication by a power of two. If the resulting value does not fit, an overflow is generated.

During an arithmetic right shift, the original leftmost bit (the sign bit) is replicated to fill in all the newly vacant positions, ensuring that the sign of the number is preserved in the operation.

Performing an arithmetic left shift on the bit sequence 10110011 results in the bit sequence 01100110, with a 0 inserted at the rightmost position. This operation effectively multiplies the original value by 2.

The arithmetic right shift operation moves bits to the right and treats the operand as a signed number, extending the sign bit. This means that if the number is negative, the sign bit (1) is replicated to fill the leftmost bits after the shift.

The arithmetic shift rounds down towards negative infinity, while the standard divide instruction truncates towards zero. Therefore, the arithmetic shift is not typically used as a replacement for the signed divide instruction.

The instruction 'sal , ' performs an arithmetic shift left operation on the destination operand, filling from the right with zeros as needed.

For the 'sal , cl' instruction, the immediate value () or the value in the cl register must be between 1 and 64. Additionally, the destination operand cannot be an immediate value, and only 8-bit immediate values are allowed.

Performs an arithmetic shift right operation on the destination operand, filling from the left as needed.

The instruction 'sar , cl' requires that the or the value in the cl register must be between 1 and 64, while 'sar , ' uses an immediate value. Additionally, the destination operand cannot be an immediate in 'sar , cl'.

The result would be 01001011 after rotating the byte operand 10010110 to the right by 1 place.

Performs a rotate left operation on the destination operand.

The or the value in the cl register must be between 1 and 64, and the destination operand cannot be an immediate. Only 8-bit immediate values are allowed.

The 'ror' instruction performs a rotate right operation on the destination operand. It can take either an immediate value (between 1 and 64) or a value from the 'cl' register, but the destination operand cannot be an immediate value itself.

Assembly language control structures are more limited than high-level language structures. For instance, high-level constructs like IF-THEN-ELSE do not exist in assembly. Instead, assembly provides unconditional and conditional jumps to implement these control flows.

A program label serves as a target location for control statements, allowing the program to jump to specific points in the code, such as the start of a loop, enabling re-execution of code segments.

Labels must start with a letter, followed by letters, numbers, or the symbol '_', and must be terminated with a colon (':'). Non-letter characters can be used to start labels, but they typically convey special meaning and should generally be avoided. Labels are case sensitive and can only be defined once in a program.

Unconditional control instructions provide a jump to a specific location in the program denoted by a label. The target label must be defined exactly once and must be accessible and within scope from the originating jump instruction.

1. Compare Instruction: This instruction compares two operands and stores the results in the rFlag registers.
2. Conditional Jump Instruction: This instruction will jump or not jump to the provided label based on the result of the previous comparison operation.

The 'jmp' instruction is used to jump to a specified label in the program. The label must be defined exactly once in the program for the jump to be valid.

The general form of the compare instruction is:

cmp <op1>, <op2>

Where and are not changed and must be of the same size. Either, but not both, may be a memory operand. The operand cannot be an immediate, but the operand may be an immediate value.

The compare instruction must be immediately followed by the conditional jump instruction. If other instructions are placed between the compare and conditional jump, the rFlag register will be altered, which may lead to incorrect conditions being evaluated for the jump.

The pseudo-code if (currNum > myMax) myMax = currNum; represents a comparison operation where the program checks if the value of currNum is greater than myMax. If true, it updates myMax to the value of currNum, which can be implemented using signed conditional jump instructions in assembly language.

The 'cmp' instruction compares the value in the 'rax' register with the value at the memory location of 'myMax'. It sets the flags in the processor based on the result of this comparison, which is then used by the conditional jump instruction 'jle' to determine whether to skip setting a new maximum value.

The 'jle' (jump if less than or equal) instruction checks the result of the previous comparison. If 'currNum' is less than or equal to 'myMax', it jumps to the label 'notNewMax', effectively skipping the instruction that sets 'myMax' to 'currNum'.

Reversing the logic allows the program to skip the execution of the code that sets a new maximum when the condition is false. This is essential for implementing the correct flow of control in the program, ensuring that 'myMax' is only updated when 'currNum' is greater than 'myMax'.

An IF-ELSE structure can be represented using a combination of comparison and conditional jump instructions. For example, after comparing 'x' with 0, a conditional jump can direct the flow to either execute the division and set 'errFlg' to FALSE or set 'ans' to 0 and 'errFlg' to TRUE based on the result of the comparison.

The data types and declarations used include:

• 'TRUE' equated to 1
• 'FALSE' equated to 0
• 'x' and 'y' as signed double-words (dd) initialized to 0
• 'ans' as a signed double-word (dd) initialized to 0
• 'errFlg' as a byte (db) initialized to FALSE.

The 'cdq' instruction is used to sign-extend the value in the EAX register into the EDX register, preparing for a signed division operation with 'idiv'.

A 'jump out-of-range' error occurs when a conditional jump instruction's target label is more than ±128 bytes away. This can be resolved by reversing the logic and using an unconditional jump to reach the target label.

The code checks if the value of 'x' is zero using 'cmp dword [x], 0'. If it is zero, it jumps to the 'doElse' label, setting 'ans' to 0 and 'errFlg' to TRUE, indicating an error. Otherwise, it performs the division and sets 'errFlg' to FALSE.

A short-jump is limited to a target label within ±128 bytes from the jump instruction, while an unconditional jump (jmp) can reach any location in the code without this limitation.

In signed division, the EDX register is used to hold the sign bit of the dividend when performing the division operation with 'idiv'. It is important for ensuring the correct result when dividing signed integers.

The cmp <op1>, <op2> instruction compares <op1> with <op2>, storing the results in the rFlag register. It does not change the operands, and both operands cannot be memory. <op1> cannot be an immediate value, and <op2> cannot be a 64-bit immediate value.

The je <label> instruction causes a jump to <label> if the preceding comparison indicates that <op1> == <op2>. The label must be defined exactly once in the code.

The jle <label> instruction jumps to <label> if the preceding comparison indicates that <op1> <= <op2> for signed data. The label must be defined exactly once.

The instruction jg <label> is used for signed data. It causes a jump to <label> if the first operand (<op1>) is greater than the second operand (<op2>), based on a preceding comparison instruction. The label must be defined exactly once.

The jge <label> instruction is used for signed data to jump to <label> if the first operand (<op1>) is greater than or equal to the second operand (<op2>), based on a preceding comparison instruction. The label must be defined exactly once.

The jb <label> instruction is used for unsigned data. It causes a jump to <label> if the first operand (<op1>) is less than the second operand (<op2>), based on a preceding comparison instruction. The label must be defined exactly once.

The instruction jbe <label> is used for unsigned data. It causes a jump to <label> if the first operand (<op1>) is less than or equal to the second operand (<op2>), based on a preceding comparison instruction. The label must be defined exactly once.

The ja <label> instruction is used for unsigned data. It causes a jump to <label> if the first operand (<op1>) is greater than the second operand (<op2>), based on a preceding comparison instruction. The label must be defined exactly once.

The instruction jae <label> is used for unsigned data and allows a jump to <label> if the result of a preceding comparison indicates that ` >= **. The label must be defined exactly once in the code.

A basic loop can be implemented using a counter that is checked at either the bottom or top of the loop with a compare and conditional jump.

For example:

1. Initialize a loop counter (e.g., mov rcx, qword [1pCnt]).
2. Perform the loop operations (e.g., summing odd integers).
3. Decrement the loop counter (e.g., dec rcx).
4. Use a conditional jump (e.g., jne sumLoop) to repeat the loop until the counter reaches zero.

The sumLoop in the provided assembly code is designed to sum the odd integers from 1 to 30. It uses a loop counter (rcx) to control the number of iterations and an accumulator (rax) to keep track of the current odd integer being added to the sum.

The general format is:

loop

This instruction decrements the rcx register, compares it to 0, and jumps to the specified label if rcx is not equal to 0.

The equivalent code sets are:

Code Set 1:
loop
Code Set 2:
dec rcx
cmp rcx, 0
jne

If the rcx register is not set before using the loop instruction, it could result in looping an unknown number of times, which may generate errors during loop execution and complicate debugging.

The loop instruction is limited to the rcx register and only counts down. Additionally, if nesting loops is required, it can cause conflicts unless the rcx register is saved and restored as needed for the inner loop.

The loop instruction can be utilized by setting the rcx register as a loop counter, performing operations within the loop, and using the loop instruction to repeat the operations until rcx reaches 0.

The loop instruction decrements the rcx register and jumps to a specified label if rcx is not equal to 0. The label must be defined exactly once in the program.

represents a register operand, meaning the operand must be a register.

indicates a destination operand, which may be a register or memory, and its contents will be overwritten with the new result based on the specific instruction.

The 'Sum of Squares' program computes the sum of squares from 1 to a specified value n. For example, for n = 10, it calculates the sum as 1² + 2² + ... + 10² = 385.

refers to an immediate value that may be specified in decimal, hex, octal, or binary formats.

These notations indicate register operands with specific size requirements, where reg8 is a byte-sized register, reg16 is a word-sized register, reg32 is a double-word sized register, and reg64 is a quad-word sized register.

When the destination register operand is of double-word size and the source operand is also of double-word size, the upper-order double-word of the quadword register is set to zero. This applies only when the destination operand is a double-word sized integer register.

The mov <dest>, <src> instruction copies the source operand to the destination operand. Key points include:

1. Both operands cannot be memory.

2. The destination operand cannot be an immediate value.

3. Both operands must be of the same size.

4. For double-word destination and source operands, the upper-order portion of the quadword register is set to 0.

lea <reg64>, <mem>

where <mem> → [address]

The general form of the integer addition instruction is 'add <destination>, <source>'.

The 'dec' instruction performs the same operation as the 'sub' instruction with a source operand of 1, effectively achieving the same result as using 'sub , 1'.